As described in the above-referenced '168 application, because of their ability to transport signals over a very wide bandwidth, fiber optic communication systems are currently being installed to replace conventional metallic cable networks. In a typical fiber optic system, for a one-way transmission path, serial digital data and its associated clock are coupled to an electro-optic transmitter, which generates an optical signal that replicates the serial digital data stream, with the clock embedded in the data. At the opposite (far) end of the fiber optic link, an opto-electronic receiver processes the received serial digital signal stream, to extract the clock and recover the data.
One of the advantages of the wide band characteristics of optical fiber networks is their ability to transport a variety of broadband signals and their flexibility in the choice of data rates for transporting serialized digital data. However, at relatively high data rates (e.g. those above ten and on the order of several hundred MHz or higher, for example), the limited performance capabilities of readily available and less costly electronic circuits and components (which currently do not operate with picosecond response times required for high data rate signals) has required the use of sophisticated signal processing to embed the clock with the data and recover the clock signal from the serial digital data stream.
One proposal to alleviate this requirement and allow use of reasonably priced signal processing equipment involves encoding the data with a reduced complexity encoding scheme (such as biphase-S encoding). However, such an encoding scheme also mandates that the transmitter and receiver equipment be data rate-specific. For biphase encoding, in which continuous 1 and 0 patterns are encoded in accordance with biphase-S encoding rules, without a priori knowledge of the data pattern, the bit rate cannot be accurately determined. As a result, it is necessary to use bit rate specific transmitter and receiver components.
The invention described in the '168 application, now '749 patent describes a data rate estimation-based clock recovery scheme, that enables serial digital data communications to be conducted over a high bandwidth link (optical fiber) at a wide range of data rates (e.g. 10-300 Mb/s), so that the receiver may automatically recover the clock signal embedded in the digital data stream, but without a priori knowledge of the data pattern. In accordance with the clock recovery scheme of the '168 application, now U.S. Pat. No. 5,838,749, advantage is taken of a pre-scramble encoding scheme described in the U.S. Pat. No. 5,410,600 to J. Toy, entitled: "Pre-scramble encoding method and apparatus for digital communication," issued Apr. 25, 1995, assigned to the assignee of the present application and the disclosure of which is incorporated herein, to derive a relatively close or `macro` estimate of the frequency of the embedded clock signal, that is within a few percent of the embedded clock frequency.
In particular, diagrammatically illustrated in FIG. 1, a variable bit rate estimator 11 is coupled to a serial data bus 13 carrying a digital data stream having a `to be determined` data rate, which falls somewhere in an extended data rate range, as output by an opto-electronic receiver (not shown). The variable bit rate estimator 11 counts positive-going transitions in a divided-down version of the serial bit stream, to produce a multibit code representative of a `relatively close` estimate (within a few percent) of the embedded data rate. The multibit code may be appropriately scaled to accurately estimate the rate of many different categories of NRZ serial data, including (but not limited to) pseudorandom sequences, SONET and SDH formatted data streams and 8B10B block-encoded data.
The data rate estimate code output by variable bit rate estimator 11 is coupled to a direct digital synthesizer and range selector controller 17, which operates on a first parsed segment (comprising a plurality of most significant bits) of the bit rate estimate code to set the output of a very precise numerically controlled oscillator within a direct digital synthesizer (DDS) 19. A divide-by-N divisor is used to define the divisor value of an octave divider within an `inner` phase locked loop (PLL) 21, through which a scaled-up frequency derived from the precision reference clock signal generated by DDS 19 is scaled into a selected range of frequencies for deriving a variable bit sync clock signal, that is applied to a digital phase detector 25. A second parsed segment (a group of least significant bits) of the bit rate estimate code is used by the controller 17 to generate a multi-bit DDS control word (and associated write control signals) representative of the frequency to be generated by a very precise numerically controlled oscillator within the DDS 19.
The controller 17 is also coupled to receive a clock signal output by a precision crystal clock generator 27 and to a sync loss signal line 31 from downstream decoder circuitry. In response to acquiring and locking the embedded data clock (RCLOCK), the logic level on a sync loss line 31 from the downstream decoder circuitry changes state, disabling the clock acquisition mechanism, and causing the bit rate synchronizer to switch to tracking mode. The loss of sync signal is also coupled to a loop filter sweep generator 33 which, until clock acquisition, continuously generates a sawtooth signal for sweeping the output voltage of an analog loop filter 34 over a range that encompasses the frequency uncertainty of the bit rate estimate produced by the bit rate estimator 11.
An internal timing and control logic circuit is operative to scale the clock down for use by an analog-to-digital converter 35. The controller 17 also periodically supplies a gate pulse signal on line 18 to the variable bit rate estimator 11. In response to the variable bit sync clock signal generated by PLL 21, the digital phase detector 25 of a second, `outer` phase locked loop clock recovery feedback path is operative to generate a VBSCLOCK output signal and a VBSDATA data stream. The digital phase detector 25 also couples filter control signals to analog loop filter 34 of the `outer` phase locked loop clock recovery feedback path.
In operation, until lock is achieved, the logic level of a loss of sync signal on line 31 causes the loop filter sweep generator 33 of the outer phase locked loop to continuously generate a sawtooth waveform signal, for sweeping the output voltage of analog loop filter 34 over a range of operation that encompasses the frequency uncertainty of the bit rate estimate produced by bit rate estimator 11. The analog output of the loop filter 34 is converted by analog-to-digital converter 35 into a digital code, and is summed with a code from a look-up table to produce an output code that is used to control the frequency produced by a precision numerically controlled frequency generator of DDS 19.
The output of the DDS 19 is an extremely stable and precise clock current within the operational range of its numerically controlled oscillator. The octave of precision tuning range is sufficiently wide as to enable the frequency of the outer phase lock loop to sweep through the range of data rate variation corresponding to the embedded clock signal resolution, until the variable data rate sync clock signal generated by the inner phase lock loop 19 coincides with the embedded clock signal in the digital data. This signal is coupled to downstream circuitry to recover the data.